1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a flash memory capable of non-volatile data storage and a method of data write in the same.
2. Description of the Background Art
Conventionally, in storing data in a flash memory capable of non-volatile data storage, in a data write sequence, information of data “0” or “1” can be stored by applying a program pulse to a memory cell transistor of a memory cell in accordance with externally input data and varying a threshold voltage of the memory cell transistor utilizing channel hot electron (CHE) or Fowler-Nordheim (FN) tunneling.
In order to confirm whether storage of information of desired data has been performed or not, in the data write sequence, verify determination for determining whether desired data has been written or not is performed by performing data read after data write, and the program pulse is applied again (verify write) until it is determined that desired data has been written, that is, until verify passes. Specifically, a threshold voltage for determination (also referred to as program verify) is provided between a threshold voltage corresponding to data “0” and a threshold voltage corresponding to data “1”, and to which side the threshold voltage of the memory cell transistor has shifted is determined. For example, it is assumed in the present example that the threshold voltage corresponding to data “0” is lower than program verify and the threshold voltage corresponding to data “1” is higher than program verify. It is assumed herein that data write and verify write in which the program pulse is applied to the memory cell transistor are collectively also referred to as program write.
According to a general data write sequence, the program pulses are applied again to data write target bits, that is, a plurality of memory cell transistors for which program write is performed in parallel, until verify of all memory cell transistors passes, for example, until the threshold voltages of the memory cell transistors are shifted to a level not lower than program verify.
Here, for example, if a bit (memory cell transistor) latest in the shift of the threshold voltage is present, the program pulse should be applied also to that bit a plurality of times until the threshold voltage thereof is shifted to the level not lower than program verify. Namely, the number of data write target bits into which data should be written increases, threshold voltages of the memory cell transistors are distributed over a wider area.
FIG. 8 illustrates spread of distribution of threshold voltages of memory cell transistors.
FIG. 8 shows threshold voltage Vth distribution (a) when the number of bits to be verified is small in an identical data write sequence.
In addition, FIG. 8 shows threshold voltage Vth distribution (b) when the number of bits to be verified is great in an identical data write sequence.
As can clearly be seen from comparison of threshold voltage Vth distributions (a) and (b) with each other, when the number of bits to be verified is great, threshold voltages Vth are distributed over a range wider than when the number of bits to be verified is small.
In addition, FIG. 8 shows threshold value distribution (c) in an example where a bit extremely late in the shift of threshold voltage Vth is present when the number of bits to be verified is great in an identical data write sequence. Here, a sign “x” represents a bit late in the shift of threshold voltage Vth. In such a case, as the program pulse is applied a plurality of times until program verify of the bit latest in the shift passes, distribution of threshold voltages Vth is significantly distant from a program verify threshold voltage Vthp.
From a point of view of spread of distribution of threshold voltages Vth of memory cell transistors, this means that a memory cell transistor of which threshold voltage Vth is in a high region is great in a shift amount of threshold voltage Vth.
In other words, deterioration of a memory cell transistor great in the shift amount is more likely because an amount of electrons or holes passing through an insulating film is great, and reliability of the memory cell transistor may not be compensated for.
Therefore, a technique to perform program write separately for data write target bits into which data should be written has been disclosed. Specifically, U.S. Pat. No. 6,157,983 shows a technique to divide a memory array into a plurality of sub arrays and performing program write in parallel for respective sub arrays.
The publication above, however, shows an example where the memory array is divided into the plurality of sub arrays and program write is performed in parallel for respective sub arrays. Here, if program write is performed at a time on the entire sub arrays (entire mat), an amount of current fed at a time (write current amount) becomes great.
In particular, when program write into a flash memory is performed, program write by applying a high voltage (for example, 7V) and injecting channel hot electron (CHE) is performed. Therefore, supply capability of a charge pump boosting a normal power supply voltage VDD (for example, 1.5V) is important. In this regard, if the amount of current (amount of write current) fed at a time is great, supply capability of the charge pump should inevitably be great and a layout area of the charge pump is made larger.
From the viewpoint of noise, in general, as more current is fed, voltage drop due to parasitic resistance or coupling noise due to parasitic capacitance is caused.
FIG. 9 illustrates voltage drop due to parasitic resistance when a current i is simultaneously fed to a plurality of memory cell transistors.
FIG. 9 exemplarily shows eight memory cells (memory cell transistors) MC on which program write is performed in parallel, and current i passes through each memory cell transistor MC here. Resistor R represents parasitic resistance or the like.
Here, when current i flows through eight memory cells in parallel, for example, a potential difference by 36i×R is produced between a D point and an ideal GND, and GND may increase by 36i×R.
Namely, with the increase in ground voltage GND, variation in current i that flows through the memory cell transistors may be caused between the memory cell transistor corresponding to the D point at the right end of the page and the memory cell transistor corresponding to the left end of the page.
Therefore, when program write is performed at a time on the entire sub arrays (entire mat), the number of data write target bits for which program write is to be performed in parallel is increased. Consequently, ground voltage GND may be raised and variation in write may be caused.
FIGS. 10A and 10B illustrate coupling noise between signal lines.
Referring to FIG. 10A, a configuration in which drivers DR1 and DR2 are provided on opposing ends of a signal line PA and drivers DR3 and DR4 are provided on opposing ends of a signal line PB is shown here.
Specifically, an example where a signal is transmitted from driver DR1, DR3 in a preceding stage through signal line PA, PB to driver DR2, DR4 in a subsequent stage is shown.
As shown in FIG. 10B, when driver DR1 drives the signal from “L” level to “H” level via signal line PA, a voltage level of signal line PB is raised in accordance with a parasitic capacitance CA between signal line PA and signal line PB. That is, coupling noise is produced.
Therefore, when program write is performed at a time on the entire sub arrays (entire mat), coupling noise level becomes higher and resistance to noise may lower.